Getting high accuracy in standalone is difficult, which is why I like GPS disciplined oscillators. I have built some with a basic deviation from correct frequency of ±2 or 3 parts per billion and if used as a timer less than a microsecond for as long as you like (because the oscillator is locked long term to the GPS, which is locked to NIST, which is about as accurate as it gets).
Your method seems very indirect. I would start with binary 32,768 in 2 bytes followed by 4 zero bytes.
Each time the ADC is read, add or subtract a temperature compensation to that. Then divide the desired frequency into the 6 byte number, the top two bytes say how many 32768 whole interrupts are required, the remaining 4 bytes are a residual.
In the oscillator IRC, subtract 1 from a copy of the whole interrupt count until it hits zero. At that point, load a timer to initiate the output pulse, add the residual to a 4 byte accumulator, when the accumulator has a carry out then add 1 to the whole interrupt count to make the copy for the next count down. There is a conversion required to convert residual to a timer value that equates to the clock frequency of the processor. This is done each output pulse so a maximum of 130 times a second, plenty of spare cycles to do it.
I don’t know what processor you used, it may have a convenient feature like the PIC16F628A where Timer 1 can trigger an output pulse without software intervention. This ensures a pulse jitter less than a microsecond.
Using a 32 bit residual will give far more accuracy than needed, the limitation will be the 32768Hz oscillator.
